E-Tech ET8 Spezifikationen Seite 87

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Chapter 3. Technical description of the hardware architecture 53
3.7.3 Memory RAS
IBM BladeCenter JS23 and JS43 Express supports Memory Scrubbing, ECC,
Chipkill Correction and Bit Steering. You can find more details about these and
other POWER Systems RAS technologies in the following white papers:
򐂰 IBM POWER Systems: Designed for Reliability.
http://www-01.ibm.com/common/ssi/cgi-bin/ssialias?infotype=SA&subtype=
WH&htmlfid=POW03019USEN&attachment=POW03019USEN.PDF&appna
me=STGE_PO_PO_USEN_WH
򐂰 IBM POWER Systems: Designed for Availability.
http://www-01.ibm.com/common/ssi/cgi-bin/ssialias?infotype=SA&subtype=
WH&htmlfid=POW03020USEN&attachment=POW03020USEN.PDF&appna
me=STGE_PO_PO_USEN_WH
򐂰 IBM POWER Systems: Designing and Implementing Serviceability.
http://www-01.ibm.com/common/ssi/cgi-bin/ssialias?infotype=SA&subtype=
WH&htmlfid=POW03021USEN&attachment=POW03021USEN.PDF&appna
me=STGE_PO_PO_USEN_WH
3.8 I/O subsystem
In this section we will discuss the I/O subsystem of JS23 and JS43 blades.
3.8.1 PCI express
Both IBM BladeCenter JS23 and JS43 Express has support for PCI-Express
(PCI-e) cards only. Each planar has connectors for one PCI-e High Speed
Daughter Card (HSDC), and one PCI-e Combinational I/O vertical Expansion
(CIOv) Card.
PCI-e is the successor to Peripheral Component Interconnect (PCI) and PCI-x
bus systems, realized by point-to-point implementation with the following general
I/O interface standards:
򐂰 Point-to-point serial interconnect with packetized, layered protocol
򐂰 2.6 Gbits per pin pair in each direction (speed scale in future generations)
򐂰 Dual simplex connection
򐂰 Scalable bus widths
򐂰 Embedded clocking technique using 8-bit/10-bit encoding
򐂰 Isochronous data transfer support
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